1. Field of the Invention
This invention relates to a panel structure of plasma display panels.
The present application claims priority from Japanese Application No. 2002-368019, the disclosure of which is incorporated herein by reference.
2. Description of the Related Art
In recent years, plasma display panels (hereinafter referred to as “PDP”) have been becoming prevalent as a large-sized and slim color screen display.
PDPs broadly fall into three broad types: a reflective surface discharge type in which display electrode pairs are formed on one of two substrates facing each other with the discharge space in between, and addressing electrodes and phosphor layers are formed on the other substrate; a opposite discharge type in which ones in each display electrode pair are formed on one of two substrates, and the other display electrodes in each display electrode pair and addressing electrodes are formed on the other substrate; and a type in which display electrode pairs and addressing electrodes are formed on one of two substrates.
FIG. 1 is a front view illustrating the structure of a conventional PDP of a reflective surface-discharge type out of the foregoing three discharge types. FIG. 2 is a sectional view taken along the V—V line in FIG. 1.
Referring to FIGS. 1 and 2, a plurality of display electrode pairs (X, Y) each forming a display line L are arranged on the rear surface of a front substrate 1, and covered with a dielectric layer 2. The rear surface of the dielectric layer 2 is covered by an MgO made protective layer 3.
Each of the display electrodes X, Y is constituted of transparent electrodes Xa, Ya and a bus electrode Xb, Yb. Each of the transparent electrodes Xa, Ya is formed of an ITO-made transparent conductive film, and the transparent electrodes Xa and Ya in each display electrode pair are placed on opposite sides of a discharge gap g. The bus electrode Xb, Yb is formed of a metal film to assist the electrical conductivity of the associated transparent electrodes Xa, Ya lined up along and connected to the bus electrode at regular intervals.
A plurality of addressing electrodes D each extend in a direction at right angles to the display electrode pair (X, Y) and are arranged in parallel on the screen-side surface of a back substrate 4. The addressing electrodes D are covered by an addressing electrode protective layer 5.
On the addressing electrode protective layer 5, a partition wall 6 is formed and shaped in a grid form constituted of transverse walls 6A each extending in a row direction (the right-left direction in FIG. 1) and vertical walls 6B each extending in a column direction (the up-down direction in FIG. 1). The partition wall 6 partitions the discharge space, formed between the paired transparent electrodes Xa, Ya and the addressing electrode D lying opposite the paired transparent electrodes Xa, Ya, into discharge cells C.
In each discharge cell C, a red-, green- or blue-colored phosphor layer 7 is formed and overlaid on the side faces of the partition wall 6 and the addressing electrode protective layer 5. The primary three colors, red, green and blue colors, are applied to the individual phosphor layers 7 in order.
The front substrate 1 and the back substrate 4 configured as described above are placed in parallel on the opposite sides of the discharge space. The discharge space between the front substrate 1 and the back substrate 4 is filled with a discharge gas made by mixing neon, xenon and the like (Xe—Ne type gas).
To generate an image on the PDP, first, an addressing discharge for selecting the discharge cells for emitting light (light emission cells) is produced selectively between the addressing electrode D and the display electrode Y. Then, a discharge-sustaining pulse is applied alternately to the display electrodes X and Y, whereby a display discharge is caused between the display electrodes X and Y in the light emission cell.
In order to enhance the luminous efficiency of the display discharge in each discharge cell C for improving the brightness on the screen, the PDPs designed as described above adopt some methods: e.g., an increase of the height of the partition wall 6 to increase the area of the reflection face of the phosphor layer 7 which is formed on the side faces of the partition wall 6; an increase of the proportion of xenon gas which is included in the discharge gas filling the discharge cell C; and an increase of the film thickness of the dielectric layer 2 covering the display electrode pairs (X, Y).
However, such a simple increase in the height of the partition wall, the proportion of xenon gas in the discharge gas, or the film thickness of the dielectric layer 2 for improvement in the luminous efficiency of the display discharge inside the discharge cell C, leads to a decrease in the margin of voltage of the data pulse applied to the addressing electrode D or of a scanning pulse applied to the display electrode Y, because an addressing discharge is caused between the addressing electrode D and the display electrode Y across the discharge space.
This decrease produces a need for raising the voltage of the data pulse or scanning pulse for setting a high starting voltage for the addressing discharge. This in turn produces a need for increasing the resistance, to high voltage, of an addressing driver IC for outputting a data pulse to the addressing electrode and of a scanning driver IC for outputting a scan pulse to the display electrode Y. These needs raise new problems of a resultant increase in production costs, creating an obstacle to realizing the saving of power by the PDP, and the like.
Further, PDPs typically adopt drive techniques, called “a subfield method”, for increasing the number of levels of luminance gradation representation to enable the displaying of an image in a gray scale in accordance with an incoming image signal.
In the subfield method, the greater the number of levels of luminance gradation representation, the greater the number of subfields in a frame. Therefore, an increased number of subfields are required for forming a high-quality image. In this event, in view of the fact that a display time period for a frame is predetermined, a time period of light emission in each subfield is shortened to reduce the brightness on the screen, leading to a need for increasing the luminous efficiency in each display discharge.
As a result, in the PDPs driven by the subfield method, especially, the foregoing problems become significantly important.